Circuit Techniques for Leakage Reduction
نویسندگان
چکیده
13.
منابع مشابه
A New Circuit Scheme for Wide Dynamic Circuits
In this paper, a new circuit scheme is proposed to reduce the power consumption of dynamic circuits. In the proposed circuit, an NMOS keeper transistor is used to maintain the voltage level in the output node against charge sharing, leakage current and noise sources. Using the proposed keeper scheme, the voltage swing on the dynamic node is lowered to reduce the power consumption of wide fan-in...
متن کاملModeling and Simulation of High Level Leakage Power Reduction Techniques for 7T SRAM Cell Design
In this paper, the process of 7T SRAM cell is analyzing and also exploring the circuit topologies, high level leakage power reduction techniques and cell parameters. The first segment contains the information about process of the 7T SRAM cell like write operation and read operation. Second segment of this paper characterize high level the leakage power reduction techniques, containing the infor...
متن کاملLeakage Power Reduction Through Hybrid Multi-Threshold CMOS Stack Technique In Power Gating Switch
In this paper Two Hybrid digital circuit design techniques are produced as Hybrid MultiThreshold CMOS complete stack technique and Hybrid Multi-Threshold CMOS partial stack technique for reducing the leakage power dissipation in mode transistion.Tri-modal switch are performance depends on these two techniques reduce the leakage power dissipation. These technique are implemented in the CADENCE v...
متن کاملFine-Grain Dynamic Leakage Reduction
Previous work in leakage current reduction for digital circuits can be divided into two main categories: static design-time selection of slow, low-leakage transistors for non-critical paths and dynamic deactivation of fast leaky transistors on critical paths. Leakage power is dominated by critical paths, and hence dynamic deactivation of fast transistors could potentially yield large savings. W...
متن کاملNew Hybrid Digital Circuit Design Techniques for Reducing Subthreshold Leakage Power in Standby Mode
In this paper, four new hybrid digital circuit design techniques, namely, hybrid multi-threshold CMOS complete stack technique, hybrid multi-threshold CMOS partial stack technique, hybrid super cutoff complete stack technique and hybrid super cutoff partial stack technique, have been proposed to reduce the subthreshold leakage power dissipation in standby modes. Techniques available in literatu...
متن کاملAnalysis and Mitigation of Cmos Gate Leakage
Conventional leakage reduction techniques focus primarily on sub-threshold leakage mitigation, while neglecting the effect of gate leakage current. This work focuses on understanding gate leakage current and developing circuit techniques for total leakage minimization. We present an efficient technique for gate leakage of CMOS circuits. Input vector control and circuit reconfiguration technique...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
عنوان ژورنال:
دوره شماره
صفحات -
تاریخ انتشار 2005