Toward Automatic Test Pattern Generation for VHDL Descriptions

This paper describes an approach for defining a model for the VHDL descriptions which can be used for test generation purpose. The VHDL description can be transformed to this model by semantic preserving transformations without lost of information needed for test generation purpose. Together with the model definition a unified fault model is defined which can be easily related to well known fault models defined on different levels of hardware abstraction (such as stack-at-0/1, wrong function selection and controller state selection fault). Finally, a discussion about possible test generation procedures based on the model is included. This work has been supported by the Swedish National Board for Technical Development (STU). Also in Proceedings of the EURO-VHDL 91 Sweden, Stockholm, September 8-11, 1991