Heuristics and Experimental Design for Bigraph Crossing Number Minimization

The bigraph crossing problem, embedding the two vertex sets of a bipartite graph G = (V0; V1; E) along two parallel lines so that edge crossings are minimized, has application to circuit layout and graph drawing. We consider the case where both V0 and V1 can be permuted arbitrarily | both this and the case where the order of one vertex set is xed are NP-hard. Two new heuristics that perform well on sparse graphs such as occur in circuit layout problems are presented. The new heuristics outperform existing heuristics on graph classes that range from application-speci c to random. Our experimental design methodology ensures that di erences in performance are statistically signi cant and not the result of minor variations in graph structure or input order.