A Noble Design of Energy Recovery Flip-Flops

The power consumption of the clock tree dominates over 40% of the total power in high performance VLSI designs. Hence, low power clocking schemes are promising approaches for low power design. We propose energy recovery clocked flip-flops that enable energy recovery from the clock network, resulting in significant energy savings. These flip-flops operate with a single-phase sinusoidal clock which can be generating with high efficiency. In Cadence 180nm CMOS technology, we implemented these energy recovery clocked flip flops through an H tree clock network driven by a resonant clock generator to generate a sinusoidal clock. The proposed flip-flops exhibit more than 80% delay reduction, 47% power reduction, as compared to the conventional energy recovery flip-flop. Simulation results show a power reduction of 90% on the clock tree and total power saving of up to 80% as compared to the conventional square wave clocking schemes and flip flops. In this paper, we also propose clock gating solution for the energy recovery clocked flip flops reduces their power and delay. A pipelined array multiplier is designed which show a total power savings of 25%-69% as compared to the same multiplier using conventional square wave clocking scheme and corresponding flip-flops.