Coprocessing Architecture in System-on- programmable-chip for Monte Carlo Simulation

Monte Carlo simulation is mainly done in computer clusters, supercomputers or computers coupled with hardware accelerators. These processing methods are sufficiently fast; however, this speed comes at the expense of physical area and power consumption. The current study aims to use System-OnProgrammable-Chip (SOPC) to accomplish the same task but using a smaller physical area. The SOPC approach takes on a coprocessing architecture to execute a Monte Carlo algorithmbased random walk on boundary (WOB) method to calculate unit cube capacitance. A time extrapolation is performed on the processing rate of the coprocessor to reveal a performance that is comparable to a 1.3 GHz Pentium 4 desktop computer. The performance results can be attributed to a streaming interface which connects the random number generator source and the coprocessor. Keywords-coprocessing; SOPC; Monte Carlo; random walk on boundary;