Word-level Formal Verification Using Abstract Satisfaction

With the ever-increasing complexity of hardware (HW) and SoC-based designs for mobile platforms, demand for scalable formal verification tools in the semi-conductor industry is always growing. The scalability of hardware model checking tools depends on three key factors: the design representation, the verification engine, and the proof engine. Conventional SAT-based bit-level formal property checking tools for hardware, as shown in the top flow of Figure 1, converts the design into a netlist, typically represented using And-Inverter graphs (AIGs). These tools can not exploit the word-level structure of designs given at the register transfer level (RTL). Over the last decade, formal hardware verification tools have therefore implemented a word-level representation of the transition relation, typically represented using BLIF format or tool-specific word-level formats, thus enabling the use of modern solvers for Satisfiability Modulo Theories (SMT). However, the performance of word-level symbolic execution engine is determined by the level of abstraction of the symbolic expressions and the power of the rewrite engines used by the SMT solvers. State-of-the-art bitlevel and word-level formal verification tools scale up to block level or small IP level circuits. These tools generally do not scale to large IPs, subsystems, or full SoC designs. Figure 1 presents a conventional bit-level hardware/software co-