Ultrafast Temperature Profile Calculation in Ic Chips

One of the crucial steps in the design of an integrated circuit is the minimization of heating and temperature non-uniformity. Current temperature calculation methods, such as finite element analysis and resistor networks have considerable computation times, making them incompatible for use in routing and placement optimization algorithms. In an effort to reduce the computation time, we have developed a new method, deemed power blurring, for calculating temperature distributions using a matrix convolution technique in analogy with image blurring. For steady state analysis, power blurring was able to predict hot spot temperatures within 1°C with computation times 3 orders of magnitude faster than FEA. For transient analysis the computation times where enhanced by a factor of 1000 for a single pulse and around 100 for multiple frequency application, while predicting hot spot temperature within about 1°C. The main strength of the power blurring technique is that it exploits the dominant heat spreading in the silicon substrate and it uses superposition principle. With one or two finite element simulations, the temperature point spread function for a sophisticated package can be calculated. Additional simulations could be used to improve the accuracy of the point spread function in different locations on the chip. In this calculation, we considered the dominant heat transfer path through the back of the IC chip and the heat sink. Heat transfer from the top of the chip through metallization layers and the board is usually a small fraction of the total heat dissipation and it is neglected in this analysis. INTRODUCTION As power densities in integrated circuits (IC’s) increases over time, controlling temperature is becoming an increasing integral aspect of the IC design [1]. With the increasing clock frequencies and shrinking die size, the temperature increase in IC chips can cause significant problems. The sub-threshold leakage power grows exponentially with temperature. Interconnect delay increases 5-8% per 10C temperature increase. Crosstalk noise level increases on the order of 25% when there’s 10C temperature difference between an aggressor and a victim. Furthermore, high temperature operation reduces the lifetime of an IC. Both electromigration and oxide breakdown are exponential functions of temperature. Compounding the problem is the fact that the cost of an IC’s thermal package also increases by $1 per Watt dissipated when powers are over 35-40W [2]. Therefore, efficient thermal design is becoming increasingly essential given the current trend in IC power consumption. In order to evaluate the thermal design of a proposed IC configuration, it is imperative to theoretically predict the temperature distribution of the active elements during operation to determine the maximum temperatures the chip will endure, in order to exclude designs that exceed the critical junction temperature. This analysis is further complicated considering the spatial and temporal non-uniform heating found in contemporary microprocessors, resulting in certain regions exceeding the mean operating temperature, which are known as “hot spots” [2]. Therefore, it is necessary to model a full temperature map of the IC’s surface under steady state and transient conditions for thermal analysis to identify the extreme temperatures produced by hot spots. Current methods, such as finite element analysis (FEA), use the differential heat conduction equation, )) , ( ) ( ( ) , ( ) , ( ) ( ) ( t x T x t x H t t x T x c x x x r r r r r r r r ∇ ⋅ ∇ + = ∂ ∂ λ ρ (1) where, T, H, ρ, c, and λ denote temperature, heat flux, mass density, specific heat and thermal conductivity, respectively. From a specified power map, the resulting temperature distribution can be calculated [3,4,5]. While this method is accurate, it is too time consuming to be implemented for large number of nodes representing a realistic IC and also to be used in routing and placement optimization algorithms. Therefore, an alternative method, with much faster calculation speeds, is necessary to ensure proper thermal design. Consequently, there has been a considerable amount of e ffort put forth in devising a faster method [6,7,8,9]. Travis Kemper, Yan Zhang, Zhixi Bian and Ali Shakouri Ultrafast temperature profile calculation in IC chips ©TIMA Editions/THERMINIC 2006 -pageISBN: 2-916187-04-9 One proposed method is to model the IC as a network of thermal resistors and capacitors. This method has been used to accurately predict steady temperature distributions in VLSI systems in order to reduce hot spot temperatures [10]. However, this method is limited by the considerable effort necessary to model each subregion of an IC’s surface as a circuit consisting of connections through the package to the heat sink, where each layer’s thermal resistance must be found analytically or experimentally [6]. A further limitation of this method is the substantial calculation times associated with solving a complex network with large number of nodes. In this paper, we present a fast and accurate numerical method to calculate the surface temperature of an IC chip. This method is based on optical filtering technique in image processing. Blurred version of an image can be produced based on a known point spread function. After a review of the optical blurring, we will apply this technique to power dissipation map on a chip. OPTICAL BLURRING A black and white digital image consists of a matrix of numerical representations of tonal value. The process of spatial filtering replaces the value of each pixel in an image with a new value in order to achieve certain goals, such as sharpening or blurring. In the case of blurring an image, f, is convoluted with another matrix w, known as a mask, to produce the blurred image g, by the follow equation ∑ ∑ − = − = + + ⋅ = b