Fault Detection Scheme for AES Using Optimization for Mix Column

In this paper for existing concurrent structure independent fault detection schemes with new technique for the fault detection of sub bytes and inverse sub bytes using the relation between the input and output of the S-box, the formulation of mix column are implemented for AES, which results in the reduction of area coverage and power consumption along with the error coverage of greater than 99% of the existing scheme. The proposed scheme and existing scheme have been implemented on the most recent Xilinx Sparton FPGA, their area and power requirements are compared and it is proved that proposed technique makes the fault detection for AES efficient in terms of area coverage(in terms of gate count) and power