Guest Editors' Introduction: Defect-Oriented Diagnosis for Very Deep-Submicron Systems

Guest Editors' Introduction: Defect-Oriented Testing in the Deep-Submicron Era

0740-7475/02/$17.00 © 2002 IEEE September–October 2002 CMOS IC SCALING increases device/interconnect density to allow more logic on a die at higher clock rates, enhancing overall performance. Improvements in process technology enable integration on a single die of circuits with different functions that require distinct manufacturing process steps. With added constraints of reduced time to marke...

Fault Tuples in Diagnosis of Deep-Submicron Circuits

Diagnosis of malfunctioning deep-submicron (DSM) ICs is becoming more dificult due to the increasing sophistication of the manufacturing process and the structural complexity of the IC itself: At the same time, key diagnostic tusks that include defect localization are still solved using primitive models of the IC’s defects. This paper explores the use of “jault tuples” in diagnosis. Fault tuple...

Guest Editors’ Introduction: Object-Oriented Computing

On the Synthesis-Oriented characteristics of high performance, deep-submicron CMOS VLSI cell libraries

Page On the Synthesis-Oriented characteristics of high performance, deep-submicron CMOS VLSI cell libraries.

Sustaining an Industry Obsession

September–October 2002 0740-7475/02/$17.00 © 2002 IEEE DEVICE SCALING has long been an accepted mantra, even an obsession, in the semiconductor industry, and if recent predictions are true, the march of deep-submicron (DSM) devices into the nanoscale era will continue. Process and device engineers will somehow find a way to overcome the looming technical challenges, just like they always have f...