Effect of Clock and Power Gating on Power Distribution Network Noise in 2D and 3D Integrated Circuits

DEDICATION To my parents and friends v ACKNOWLEDGEMENTS I would like to thank my advisor Professor Wayne Burleson and Prof. Sandip Kundu for all their support and guidance throughout this work. Their valuable feedback helped me to focus on the topics of this research. I also would like to thank Prof. Joseph Bardin for serving on my committee and providing valuable suggestions during the course of this work. Special thanks to Sudarshan and Arunkumar for several valuable discussions we had regarding this work and other topics of common interest. I would like to thank my lab-mates Krishna, Raghavan and Vikram for their suggestions on several related topics on VLSI and for their support and encouragement. I would also like to thank the University of Massachusetts Amherst for providing a wonderful environment to conduct research. Finally I would like to thank my parents for their constant love and support. Increased budgetary constraints on power consumption in modern microprocessors has led to wide-scale adoption of both clock gating and power gating to aid in the reduction of power usage. But, gating introduces its own noise into the Power Distribution Network (PDN). In order to ensure a stable power supply, the worst-case noise from gating must be characterized to verify the integrity of the on-chip power grid. In this work, power supply noise contribution at a particular Point of Interest (POI) from clock/power gated blocks is maximized at particular time and the synthetic gating pattern that results in the maximum noise is obtained for the interval 0 to target time. To aid in the efficient estimation of the noise we utilize wavelet based analysis as wavelets are a natural way of characterizing the time-frequency behavior of the power grid. The fundamental/base wavelets are constructed using the impedance profile of the power grid constituting the frequency-domain behavior of the grid. These wavelets are used as model current sources within the gated blocks and the voltage responses of the grid at the target location from these sources is tabulated accounting for the time-domain behavior of the power grid. The final synthetic waveforms of the current sources are composed of wavelets of multiple resolutions and the waveforms are obtained via a Linear Programming (LP) formulation (for clock gating) and Genetic Algorithm based vii problem formulation (for Power Gating) which also output the gating patterns of the gated blocks and the maximum supply noise at the Point …