Challenges in Nanoscale Devices and Breakthrough

Over the past 50 years of the semiconductor industry, the size of MOSFETs has been scaled down obeying the Moore’s law: feature sizes of transistors are scaled at a rate of approximately 0.7 times every 18 months. However, as CMOS technology approaches nanoscale region, researchers face with critical technology barrier known as short channel effect. While the gate voltage fully controls the channel conduction state in an ideal MOSFET, the drain voltage begins to give more influence on the channel potential in a nanoscale MOSFET. It leads to the dependence of the threshold voltage on the channel length and width, drain induced barrier lowering (DIBL), degradation of the subthreshold swing, and punchthrough. Fig. 1 summarizes some requirements of the state-ofthe-art CMOS technology. In order to solve these issues, holding present bulk planar CMOS technology, many studies have been successfully performed down to 45 nm technology node [1], [2]. However, CMOS scaling trend in near future will not be as straightforward as it has been in the past due to fundamental material and process limits are imminent. To address challenges in nanoscale devices, recent researches are divided into four categories as below. Same structure and same materials Same structure but new materials New structure but same materials Novel device concepts This paper will focus on reviews of abovementioned topics including some excellent works performed in our research group.