Optimizing the Number of Bits/Stage in 10-Bit, 50Ms/Sec Pipelined A/D Converter Considering Area, Speed, Power and Linearity

Pipeline ADCs are becoming popular at high speeds and with high resolution. This paper discusses the options of number of bits/stage conversion techniques in pipelined ADCs and their effect on Area, Speed, Power Dissipation and Linearity. The basic building blocks like op-amp, Sample and Hold Circuit, sub converter, DAC, Residue Amplifier used in every stage is assumed to be identical. The sub converters use flash architectures. The design is implemented using 0.18 m CMOS technology and uses 3.3V power supply. The paper implements a 10 bit 50MSPS pipelined ADC using 1, 1.5, 2, 3, 4 and 5 bits/stage conversion and compares them with respect to Area, Speed. Power and Linearity. The paper concludes by stating that 2bits/stage is optimum for a pipelined ADC and to reduce design complexity we can go up to 3 bits/stage. Keywords—1.5 bits/stage, Conversion Frequency, Redundancy Switched Capacitor Sample and Hold Circuit.