CMOS Image Sensor Architecture for Primal-Dual Coding

A CMOS image sensor architecture for primal-dual coding (PDC), the developed image sensor and the sensing side of the system, as well as preliminary sensor test results are presented in this paper. The architecture proposed in this work uses pixels with the embedded 2-bit latches which are responsible for the pre-loading and storing of the exposure codes. The subsequent exposure code (mask) can therefore be loaded while the current mask is being used for exposure, resulting in a pipelined coding operation which does not interfere with the pixel exposure time. The mask loading is done serially via a vertical metal line (one line per-column), making both the imager architecture and the pixel array scalable towards high pixel resolutions. The sensor is designed using a 0.35μm image sensor optimized CMOS process resulting in the total pixel pitch of 25μm. The pixel includes a photo-gate based photodetector, two 1-bit latches, required logic gates, two charge collection buckets (floating diffusions) and corresponding symmetric readout with two source-followers (one for each bucket), resulting in a pixel fill-factor of 20.5%. Every pixel column features a programmable gain amplifier whose outputs are time-multiplexed over 3 analog output pads. Analog-to-digital conversion is performed off-chip by 3×16-bit ADCs. The 60×80 pixel imager consumes 7mW of power while operating at 25 fps. The sensor measurement results show that the loading of the complete PDC mask for the whole array can be performed in 30μs, resulting in a large number of masks that can be applied during a single exposure time, therefore creating a very promising platform for an effective and optimal use of PDC.