Minimization Algorithms for Multiple-Valued Programmable Logic Arrays

نویسندگان

  • Parthasarathy P. Tirumalai
  • Jon T. Butler
چکیده

We analyze the performance of various heuristic algorithms for minimizing realizations of multiple-valued functions by the newly developed CCD 191 and CMOS [W] programmable logic arrays. The functions realized by such PLA's are in sum-of-products form, where sum is ordinary addition truncated to the highest logic value, and where product represents the MIN operation on functions of the input variables which are the interval literal operations. We compare three previously published heuristics, Pomper and Armstrong [14], Besslich [3], and Dueck and Miller [6], over sets of random and random symmetric functions. We show an exact minimization method that is a tree search using backtracking. A considerable reduction in the search space is achieved by considering constrained implicunt sets and by eliminating some implicants altogether. Even with this improvement, the time required for exact minimization is extremely high when compared to all three heuristics. We also examine the case where only prime implicunfs are considered and show that such implicants have marginal value compared to constrained implicant sets. Our basis of comparison is the average number of product terms. We show that the heuristic methods are reasonably close to minimal and produce nearly the same average number of product terms. Interestingly though, there is surprisingly little overlap in the set of functions where the best realization is achieved. Thus, there is a benefit to applying all three heuristics to a given function and then choosing the best realization. HE minimization of sum-of-products expressions in binary T logic has received considerable attention for over 30 years. The complexity of the problem has been known for almost as long. In 1965, Gimpel [7] showed that any instance of the set covering problem is an instance of sum-of-products extraction. In 1972, Karp [8] showed that the set covering problem is NP complete; thus, so also is sum-of-products extraction. The best known algorithm then requires exponential time. This is a real barrier; it precludes the exact minimization of functions with even a moderately low number of inputs, e.g., 20. As a result, considerable effort has been devoted to heuristic minimization methods. For example, among the Berkeley VLSI tools is ESPRESSO-IIC [4], a C program that minimizes binary functions by a set of operations on the prime implicants. Recently, there has been considerable interest in multiple-and at least one implemented [9]. We know of three heuristic multiple-valued sum-of-products minimization algorithms. All three use the direct cover …

برای دانلود رایگان متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Multiple-Valued Minimization to Optimize PLAs with Output EXOR Gates

This paper considers an optimization method of programmable logic arrays (PLAs), which have two-input EXOR gate at the outputs. The PLA realizes an EXOR of two sum-of-products expressions (EX-SOP) for multiple-valued input two-valued output functions. We present techniques to minimize EX-SOPs, which is an extension of Dubrova-Miller-Muzio’s AOXMIN algorithm. We conjecture that, when n is suffic...

متن کامل

HAMLET - An Expression Compilerloptimizer for the Implementation of Heuristics to Minimize Multiple-Valued Programmable Logic Arrays*

HAMLET is a CAD tool that translates a user specification of a multiple-valued expression into a layout of a multiple-valued programmable logic array (MVLPLA) which realizes that expression. It is modular to accommodate future minimization heuristics and future MVL-PLA technologies. At present, it implements two heuristics, [2] and [8] and one MVL-PLA technology, current-mode CMOS [6] . Specifi...

متن کامل

HAMLET - An Expression Compiler/Optimizer for the Implementation of Heuristics to Minimize Multiple-Valued Programmable Logic Arrays

HAMLET is a CAD tool that translates a user specification of a multiple-valued expression into a layout of a multiple-valued programmable logic array (MVLPLA) which realizes that expression. It is modular to accommodate future minimization heuristics and future MVL-PLA technologies. At present, it implements two heuristics, [2] and [8] and one MVL-PLA technology, current-mode CMOS [6] . Specifi...

متن کامل

Output Phase Optimization for AND-OR-EXOR PLAs with Decoders and Its Application to Design of Adders

This paper presents a design method for three-level programmable logic arrays (PLAs), which have input decoders and two-input EXOR gates at the outputs. The PLA realizes an EXOR of two sum-ofproducts expressions (EX-SOP) for multiple-valued input two-valued output functions. We developed an output phase optimization method for EXSOPs where some outputs of the function are minimized in the compl...

متن کامل

Minimization of Exclusive Sums of Multi-Valued Complex Terms for Logic Cell Arrays

| The paper proposes a new layout-driven multi-level logic factorization methodology for regular arrays of two-input cells, that can nd practical applications in ne-grain FPGA design, standard cell, gate matrix layout and sub-micron technologies. A new factorization algorithm for AND/OR/EXOR logic with multi-valued literals is introduced, that has application to minimization of Logic Cell Array...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

عنوان ژورنال:
  • IEEE Trans. Computers

دوره 40  شماره 

صفحات  -

تاریخ انتشار 1991