Efficient Fpga Implementation of an Adaptive Filter for Noise Cancellation

This paper presents an efficient architecture of the Least Mean Square (LMS) adaptive algorithm implemented as a FIR filter on a reconfigurable platform. The architecture of the adaptive filter was developed with a general structure so it can be used in many applications with minimum limitations. Besides general use, the architecture has the advantage of using optimal hardware resources on the chip. The effectiveness of the proposed architecture is demonstrated on the noise cancelling application, and the performances are evaluated in terms of signal-to-noise ratio (SNR), convergence speed, mean square error (MSE) and hardware usage.