Synthesis of Read-Once Digital Hardware with Reduced Energy Delay Product

This paper presents a low power driven synthesis framework for the unique class of nonregenerative Boolean Read-Once Functions (BROF). A two-pronged approach is adopted, where the satisfiability of the functionality is first ensured at the logic level on the basis of the proposed ‘hybrid synthesis method’. The resulting circuitry is contrasted with the reduced disjunctive normal form (DNF), resulting from standard two-level synthesis tool, ESPRESSO and conjunctive normal form (CNF) expression obtained via, the conventional Tabulation method. The gate level schematics are then translated into MOS transistor descriptions via, static CMOS and stacked CMOS implementation styles. Leakage Control Transistors (LCTs) are also inserted between the pull-up and pull-down network nodes, so as to minimize the overall power consumption of the digital logic circuits designed. Furthermore, the effect of transistor re-ordering on the delay of the resulting CMOS digital designs is also investigated. The adopted synthesis procedures are all evaluated based on a common Energy Delay Product (EDP) metric. The SPICE simulation results obtained for a 350nm TSMC CMOS process are promising, as it reports 41.5% savings in EDP, 10.5% reduction in power and 17.7% decrease in delay for the proposed method, on an average, over the best of conventional methods.