A Continuous-Time Band-Pass Σ∆ Modulator Implemented in 0.35u BiCMOS using Transmission Lines

This work presents experimental results of a 6 order band-pass continuous-time sigma-delta modulator that uses transmission lines as resonators. It has been implemented in 0.35u SiGe BiCMOS technology. The modulator tolerates two clock cycles of excess loop delay and has similar clock jitter sensitivity than that of an equivalent switched capacitor solution. The ADC operates at a sampling rate of fs=184 MHz, consumes 62mW and, assuming an OSR=256, is able to convert with a maximum SNR=55dB signals centered both at 46 MHz and 138 MHz, due to its subsampling capabilities.