Timing aware power minimization in VLSI microprocessor by simultaneous multilayer wire spacing

Due to continuous technology scaling, the interconnect delay and power reduction is becoming one of the most important design challenges. In this paper, we present a novel algorithm for simultaneous multilayer interconnect spacing so that on the one hand the total power of interconnect is reduced and on the other hand, delay constraints are not violated. We first present an optimization problem and show that it is convex and therefore has unique optimal solution. Then, we develop algorithm which solves the optimization problem. The optimization we propose can be applied to individual nets as well as to large layouts due to smart layout partitioning scheme applied. We demonstrate algorithm effectiveness by showing power reduction of 5-12% of interconnect power on clips from real industrial layout of 32 nm technology node. In addition, we show relation of new optimization technique with previously reported Weighted Power-Delay Sum optimization (WPDS).