Data Word Length Reduction for Low-Power DSP Software

Data Word Length Reduction for Low-Power DSP Software Kyungtae Han Abstract The increasing demand for portable computing accelerates the study of minimizing power dissipation. Most power in processes is consumed by the switching activity of capacitance. The switching power can be reduced by not only minimizing hardware but also optimizing software. Key papers for low power techniques of hardware and software are surveyed. Power analysis and minimization techniques make it possible to optimize software power. Variable word lengths in arithmetic operations without any change of hardware can be a promising software power minimization technique. The objective of this work is to analyze and minimize power dissipation of digital signal processing (DSP) blocks at software level. Preliminary results of an array multiplier with reduced word lengths and plans are presented. This research will have contribution to prolong battery life in portable DSP applications.