Variability-Aware Modeling of Pulse Latches

In this paper we study the impact of variability on the pulse latch. Pulse (or pulsed) latch is crucial element of the current SoC designs for both delay and power consumption. The threshold voltage (Vt) fluctuations due to Random Dopant Fluctuation (RDF) and Process, Voltage, and Temperature (PVT) effects on probability of failure are discussed. We propose a modeling methodology which is not tied to a specific topology and scaleable in contrast to techniques such as Monte Carlo simulation. To estimate the probability of failure, we uniformly sample the variation space and reconstruct the Probability Density Function (PDF) for each delay path. Then we statistically calculate the lower bound of failure.