Embedded software verification in hardware-software codesign

Concurrent Embedded Real-Time Software (CERTS) is intrinsically di€erent from traditional, sequential, independent, and temporally unconstrained software. The veri®cation of software is more complex than hardware due to inherent ̄exibilities (dynamic behavior) that incur a multitude of possible system states. The veri®cation of CERTS is all the more dicult due to its concurrency and embeddedness. The work presented here shows how the complexity of CERTS veri®cation can be reduced signi®cantly through answering common engineering questions such as when, where, and how one must verify embedded software. First, a new Schedule-Verify-Map strategy is proposed to answer the when question. Second, veri®cation under system concurrency is proposed to answer the where question. Finally, a complete symbolic model checking procedure is proposed for CERTS veri®cation. Several application examples illustrate the usefulness of our technique in increasing veri®cation scalability. Ó 2000 Elsevier Science B.V. All rights reserved.