Configurable multiplier blocks for use within an FPGA
نویسندگان
چکیده
Abstract A new architecture is proposed for configurable blocks which can be used to construct a multiplier. An array of these blocks is capable of being configured to perform any 4m bits x 4n bits signed/unsigned binary multiplication. The blocks are designed to be embedded within a conventional FPGA structure to increase the functionality of the device by freeing valuable general reconfigurable resources, particularly when used in the area of image processing.
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تاریخ انتشار 1998