On Potential Fault Detection in Sequential CircuitsElizabeth

During fault simulation, an approximation frequently used in practice is to declare a fault to be detected after it has been potentially detected a predetermined number of times. This approximation may lead to declaring a fault detected when in fact the fault will not be detected during a standard test application process. We propose an alternative measure of fault detection for potentially detected faults, that is easy to compute, yet its accuracy is signiicantly higher than the measure based on the number of times a fault is potentially detected. Experimental results are shown to support the accuracy of the new measure. Fault simulation is used extensively in the test generation process to identify the faults detected by a given test. For eecient processing, fault simulators 1, 2, 3, 4] use a 3-value model in which lines may take on logic 1, logic 0, or unknown (X) values. Sequential circuits are assumed to start in an unknown state, and therefore, X values are initially assigned to all the state lines. Good design practice requires that sequential circuits be ini-tializable, either using hardware reset or synchronizing sequences. A circuit that is initializable under 3-value simulation is logically initializable, while a circuit that is initializable considering all possible individual initial states is functionally initializable 5, 6, 7]. Faults modify the circuit structure, and certain faults cause the circuit to remain in an unknown state throughout the simulation. For example, the stuck-at-0 fault on the reset line of the ip-op shown in Figure 1 prevents the ip-op from being set to a known value, and the faulty circuit remains in an unknown state. Even if the fault eeects propagate to a primary output, the value propagated by 3-value simulation will be a known 1 or 0 for the good (fault-free) circuit, but an unknown for the faulty circuit. The fault is thus declared to be potentially detected 8]. 1 0 D Q stuck-at-0 X Figure 1: Fault on ip-op reset line During testing of the actual physical device, the state lines will always take on 0 or 1 logic values. If a fault is potentially detected for several test vectors, it is likely that either a 1/0 value pair for the good and faulty circuits or a 0/1 value pair will propagate to the primary outputs. In this case, the fault will be detected. Based on this observation, some fault simulators make the approximation …