IBM Crams Power2 onto Single Chip; 8/26/96

While putting most of its emphasis on PowerPC products from its partnership with Motorola, IBM continues to maintain its own line of POWER processors. A relatively small team, in less than a year, took the eight-chip Power2 design (see 071301.PDF) and collapsed it into a single die, delivering a powerful new product. The phenomenal integration provides manufacturing cost savings and, more important, improved performance by eliminating the overhead of chipto-chip communication. The new device, dubbed P2SC, is the most complex single-chip processor yet announced. It can issue and execute six instructions per cycle, two of which can be floating-point multiply-add instructions. It supports register renaming and out-of-order execution, although only for floating-point code; also, the P2SC’s out-of-order design uses a primitive technique compared with the reorder buffers of more modern processors. The chip includes 160K of on-chip cache, more than any other microprocessor, for a total transistor count of 15 million. Putting so much onto one chip requires an advanced IC process: the P2SC is the first processor to take advantage of IBM’s 0.29-micron CMOS-6S process (see 090905.PDF). IBM Crams Power2 o P2SC Offers Incredible Memory Bandw