A Novel Shift and Add Algorithm for Low Power and Area Efficient Fir Filter

High-speed DSP systems are increasingly being implemented on FPGA hardware platforms. This trend is being fuelled by insurmountable ASIC project costs and the flexibility and reconfigurability advantages of FPGAs over traditional DSPs and ASICs, respectively. Very recently, Structured ASIC technology has yielded lower cost solutions to full custom ASIC by predefining several layers of silicon functionality that requires the definition of only a few fabrication layers to implement the required design.