A VLSI Implementation of High Sensitive Fingerprint Sensor using Parasitic Insensitive Charge Transfer Circuit

This paper implements 80x64 array high sensitive fingerprint sensor with the parasitic insensitive charge transfer circuit. The fingerprint sensor cell uses an active output voltage feedback integrator. The parasitic insensitive charge transfer circuit includes a differential amplifier and two switches to remove parasitic capacitance and transfer charge. The operation is validated by HSPICE for one-pixel and RTL simulation including logic synthesis for the full chip design on condition of 0.18μm typical CMOS process and 1.8V power. The voltage difference between a ridge and valley is about 215mV after 10 clock cycles and 367mV after 20 clock cycles. The maximum frequency of cell operation is 10MHz. The layout is performed by full custom flow for one-pixel and auto P&R for the full chip. The area of the full chip is 4943μm x 3943μm and the gate count is 542,000. The area of one-pixel is 50μm x 50μm. Pitch is 50μm and image resolution is 508dpi.