A method of reducing aliasing in a built-in self-test environment

In this paper we propose a method of reducing aliasing in built-in self-test of VLSI circuits. The method is based on the use of transition count testing. We first give a new formulation of the problem in terms of finding a test generator as opposed to solving the problem at the data compaction end. An algorithm is proposed which can be used to find a counter-based test pattern generator. This test generator tests a circuit exhaustively or pseudo-exhaustively such that the aliasing is reduced substantially provided the data compactor used is a transition counter. Experimental results are presented to substantiate these claims.