Energy-Efficient Time-Domain Vector-by-Matrix Multiplier for Neurocomputing and Beyond

We propose an extremely energy-ecient mixed-signal approach for performing vector-by-matrix multiplication in a time domain. In such implementation, multi-bit values of the input and output vector elements are represented with time-encoded digital signals, while multi-bit matrix weights are realized with current sources, e.g. transistors biased in subthreshold regime. With our approach, multipliers can be chained together to implement large-scale circuits completely in a time domain. Multiplier operation does not rely on energy-taxing static currents, which are typical for peripheral and input/output conversion circuits of the conventional mixed-signal implementations. As a case study, we have designed a multilayer perceptron, based on two layers of 10 × 10 four-quadrant vectorby-matrix multipliers, in 55-nm process with embedded NOR ƒash memory technology, which allows for compact implementation of adjustable current sources. Our analysis, based onmemory cell measurements, shows that at high computing speed the drain-induced barrier lowering is a major factor limiting multiplier precision to ∼ 6 bit. Post-layout estimates for a conservative 6-bit digital input/output N × N multiplier designed in 55 nm process, including I/O circuitry for converting between digital and time domain representations, show ∼ 7 fJ/Op for N > 200, which can be further lowered well below 1 fJ/Op for more optimal and aggressive design.