Floating-Point Analog-to-Digital Converter

To deal with the wide dynamic rage necessary for a radio receiver or corresponding applications, but to avoid impractically high resolution at high data rates, the approach of using a floating-point analog-to-digital converter (FP-ADC) has been investigated. This approach de-links the dynamic range with the resolution, and a very wide dynamic range can be achieved by an ADC with a moderate resolution. The solution for an FP-ADC presented in this thesis is to amplify the input signal in several channels using binary weighted gains. The channel output with the largest amplitude, but still within the ADC input range, will be selected for conversion. The binary weighting is obtained by dividing the input signal with passive divider and amplifying the divider outputs by identical amplifiers. The outputs from the amplifiers are sampled individually. The selected sampled signal is then converted by a pipelined ADC. The result from the selection gives the exponent and the ADC output the mantissa of the floating-point number. Issues on the specific problems of designing the proposed FP-ADC have been addressed, including a general discussion about a pipelined ADC along with its sub-blocks. A thorough investigation of the distortion in a pipelined ADC due to static mismatches and systematic errors is also presented. The result of the investigation is a general approach on how to calculate the distortion in a pipelined ADC. The distortion analyses can be performed by both analytical methods and computer simulations. A chip has been manufactured in a standard analog 0.35 μm CMOS process giving 10 bits of resolution, and a dynamic range corresponding to a 15-bit ADC. The sampling rate is 54 Ms/s using 330 mW of power.