A multi-chip pulse-based neuromorphic infrastructure and its application to a cortical model of orientation selectivity

The growing interest in pulse-mode processing by neural networks is encouraging the development of hardware implementations of massively parallel networks of Integrate-and-Fire (I&F) neurons distributed over multiple chips. Address-event representation (AER) has long been considered a convenient transmission protocol for spike based neuromorphic devices. One missing, long-needed feature of AER-based systems is the ability to acquire data from complex neuromorphic systems and to stimulate them using suitable data. We have implemented a general-purpose solution in the form of a PCI board (the PCI-AER board) supported by software. We describe the main characteristics of the PCI-AER board, and of the related supporting software. To show all the functionality of the PCI-AER infrastructure we demonstrate a reconfigurable multi-chip neuromorphic system for feature selectivity which models orientation tuning properties of cortical neurons.