An Eecient Strategy for Developing a Simulator for a Novel Concurrent Multithreaded Processor Architecture

In developing a simulator for a new processor architecture, it often is not clear whether it is more eecient to write a new simulator from scratch or whether it is better to try and modify an existing simulator. Writing a new simulator has the advantages of needing to understand only the new processor architecture itself and being the \owner" of the nal code. However, it also forces the processor architect to develop or adapt all of the related software tools, such as compilers, assemblers, and so forth. On the other hand, modifying an existing simulator and related tools can be time-consuming and error-prone since the simulator writer must learn the details of someone else's code which is, typically, not well documented. We describe the SImulator for Multithreaded Computer Architectures (SIMCA) that was developed with the primary goal of obtaining a functional simulator as quickly as possible to begin evaluating the superthreaded architecture being developed at the University of Minnesota 2, 3]. The performance of the simulator itself was important, but secondary. We achieved our goal using a technique we call process-pipelining that exploits the unique features of this new architecture to hide the details of the underlying simulator, which is based on the SimpleScalar tool set 4]. This approach allowed us to quickly produce a functional simulator whose performance was only a factor of 3.8 to 4.9 times slower than the base SimpleScalar simulator. Because of the modularity of this approach, some simple optimizations allowed us to improve its performance by a factor of two with little eeort.