A Symmetric Differential Clock Generator for Bit-Serial Hardware

Bit-serial architectures require less area but more sophisticated clocking mechanisms than their parallel counterparts. This paper presents a CMOS circuit that generates high-frequency clock waveforms for bitserial hardware. Triggered by a master clock input, the circuit outputs a fixed number of pulses followed by a completion signal. The design uses two coupled ring oscillators to produce differential outputs with aligned positive and negative transitions. This feature allows the circuit to drive transmission gates as well as shift registers with complementary enable inputs. Layout simulations in 180-nm CMOS demonstrate that the clock generator can run at 2 GHz. The circuit thus can drive a bit-serial module with a 9-cycle computation phase at 200 MHz. The power consumption is 1.66 mW in this case. The small size of the layout permits the clock generator to be replicated locally for each bit-serial module.