Area Efficient SAD Architecture for Block Based Video Compression Standards
نویسندگان
چکیده
Block based motion estimation is one of the critical task in video compression standards such as MPEG-4, H.263, H.264. The key element of the block based motion estimation algorithms is the matching criteria. SAD(Sum of Absolute Difference) is the most common matching criteria chosen in video coding because of its low complexity, good performance and ease of hardware implementation. By utilizing the concept of reversibility a novel compression array unit using reversible 4:2 compressor has been proposed. Experimental results indicate that the proposed compression unit will impose effectiveness on the SAD architecture in calculating the motion vectors with reasonable area overhead and power penalty. Keywords—Motion estimation, Sum of absolute difference, 4:2 Compressor, SAD architecture, Reversible gates.
منابع مشابه
Motion Estimation Architecture Using Efficient Adder-Compressors for HDTV Video Coding
This paper presents our high performance architecture for Motion Estimation (ME) using efficient 4-2 and 8-2 adder compressors to calculate the Quarter Sub-sampled Diamond Search (DS) block matching algorithm with Dynamic Iteration Control (QSDS-DIC) [1]. Motion estimation (ME) is the most important task in the current standards of video compression. Full Search (FS) is the most used block matc...
متن کاملVLSI Implementation of High Performance Optimized Architecture for Video Coding Standards
This study presents a fast search algorithm and its Very Large Scale Integration (VLSI) design to implement an Enhanced Diamond Search (EDS) of Block-based Motion estimation for video compression systems. The proposed algorithm reduces the number of search points with a slight increase in average Sum-of-Absolute Difference (SAD) per pixel and significant reduction in Peak Signal-to-Noise Ratio ...
متن کاملMinimum Sum of Absolute Differences Implementation in a Single FPGA Device
Block based motion estimation is one of the critical task in today video compression standards such as H.26x, MPEG-1, -2 and 4 standards. Most of the block based motion estimation algorithm are based on computing the sum of absolute differences (SAD) between corresponding elements in the candidate and reference block. In this paper a FPGA design for fast computing of the minimum SAD is proposed...
متن کاملSAD computation based on online arithmetic for motion estimation
Block-based motion estimation is one of the critical tasks in today’s video compression standards such as H.26x, MPEG-1, -2 and -4. Most of the block-based motion estimation algorithms are based on computing the sum of absolute differences (SAD) between corresponding elements in the candidate and reference blocks. In this paper, an field-programmable gate-array (FPGA) design is proposed for rap...
متن کاملLossless Image and Intra-frame Compression with Integer-to-Integer DST
Video coding standards are primarily designed for efficient lossy compression, but it is also desirable to support efficient lossless compression within video coding standards using small modifications to the lossy coding architecture. A simple approach is to skip transform and quantization, and simply entropy code the prediction residual. However, this approach is inefficient at compression. A...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
عنوان ژورنال:
دوره شماره
صفحات -
تاریخ انتشار 2013