The Design of Delay Insensitive Asynchronous 16-bit Microprocessor

In recent, asynchronous design has been resurged to exploit potential advantages of asynchronous VLSI such as; high-performance, low power consumption, timing fault tolerance and design cost reduction. This paper describes our first design and implementation of DINAMIK project which aims to show realizability of potential merits of asynchronous VLSI and to establish the design methodology. In the design, ease of design(high modularity) and delay insensitivity was especially emphasized while power consumption, performance and area optimization were ignored as the first stage of the project. To achieve our main purpose simple architecture and a pessimistic delay assumption has been selected. DINAMIK has been fabricated as a SOG using 0.6 technology.