A Novel Asynchronous ADC Architecture

In this paper, a novel architecture for asynchronous analog-digital conversion is presented, designed using the NULL Convention Logic (NCL) paradigm. This analogto-digital converter (ADC) employs successive approximation and a one-hot encoded masking technique to digitize analog signals. The architecture scales readily to any given resolution by utilizing the one-hot encoded scheme to permit identical logical components for each bit of resolution. The 4-bit configuration of the proposed design has been implemented and verified by simulation in 0.18um CMOS technology. The asynchronous ADC requires only one delay insertion to guarantee correct operation, unlike many other asynchronous designs. Furthermore, the ADC may be interfaced with either synchronous or four-phase asynchronous digital systems.