Security analysis and fault injection experiment on AES

Cryptographic circuits are often a foundation of security in nowadays systems. As a consequence, attacks on them are critical and can be used to defeat security policies. In this context, the protection against attacks is a major concern. A fault attack uses a physical perturbation of the circuit in order to obtain faulty computations. These miscomputed results can enable cryptanalysis and reveal secret data. Several cryptosystems are concerned by this type of attacks : RSA [BDL97], DES [BS97] and AES [Gir04][DLV03][PQ03]. The robustness against fault attacks must be evaluated to ensure fault tolerance and security. This can be achieved by injecting faults in the system in order to validate its behavior under fault attacks. It is possible to do this using physical fault [GKT89][AAA+90][MRMS94], but this can also be done using built-in debug mechanisms [FSK97][BPRR98]. Another approach is to use fault injection during simulation to provide robustness evalutation before silicon IC manufacturing in an relatively unexpensive manner. Simulating the circuit permits to inject fault by modifying its description [JAR+94][LH00][ZME03] or to add a custom fault injector in the design [FMR06]. Our approach is to use an unmodified description of the circuit to be very accurate regarding to the corresponding physical circuit. However, some properties of cryptographic algorithm can be used to predict the temporal sensitivity of circuits. In this paper, we propose a metric of sensitivity against fault attacks for circuits and validate it using fault injection in simulation on AES. This paper is organized as follows : the algorithm AES and its implementation is introduced in section 2. We describe our analysis of sensitivity in section 3 and apply it to AES. Then, we present our injection methodology and tool in section 4. To conclude, future work is described in section 5.