Implementation and Design of Digital System for High Frequency RFID Tag Chip

Passive RFID tag system requires low-power consumption. In this paper, the clock shutdown technology was been used to reduce power consumption and the module re-used was been used to reduce chip area. The design was been described for the digital part of RFID tag chip based on ISO/IEC15693 standard, that was including decoder, encoder, CRC generation and verification, EEPROM interface block ,the master state machine and clock management block. The detailed design scheme about the master control block, Conflict part and coding block was been given. The unique coding was been used and state machine design scheme was been used in all blocks, which would not only simplify the design, but make the design more flexible. And EEPROM RTL model was been built-in for test validation. Finally, the results were verified correctly in the specified clock frequency in device in DE2-115FPGA Altera kit using Verilog in RTL level. Copyright © 2014 IFSA Publishing, S. L.