Area Efficient and High Speed VLSI Based Pipelined 64-Point Radix-4 Mixed Architecture Design

In this paper, a new VLSI based Radix-4 FFT architecture is developed by combining the mixed radix and pipelining architectures. Proposed architecture named as “Radix-4 Combined Single Path Delay Feedback (SDF) Multipath Delay Commutator (MDC) FFT”. As the name itself, design of proposed FFT architecture is designed with the help of both SDF and MDC data flow structures. Both SDF and MDC architectures have different types of advantages based on their dataflow structures. SDF structure has advantages in improving the speed and MDC structure has advantages in reducing the low chip area & lower power consumption. In addition to developed architecture, Modified Bit Parallel Multiplier (MBPM) has been used in the place of twiddle factor multiplication. Simulation of proposed FFT architectures are evaluated by using ModelSim 6.3C and performances are validated by using Xilinx Plan-ahead Integrated Circuit (IC) vendors. Proposed new circuits will be absolutely used in Orthogonal Frequency Division Multiplexing (OFDM) and Software Defined Radio (SDR) system.