Adding a Mixed-Signal PLL to a Prime Digital ASIC

Many ASIC companies make it easy to add a PLL, offering the core as a drop-in cell on a standard-cell design or as a cell option in a gate array. However, that seemingly simple addition of a PLL cell to an all-digital ASIC can cause several problems if the ASIC designer isn’t careful. Although much of what is inside a PLL circuit is high-speed digital circuitry, the guts of the PLL include analog circuits that require thoughtful placement within the ASIC floorplan. Suddenly, that digital ASIC design has evolved into a mixed-signal ASIC design.