Predicting device performance from pass/fail transient signal analysis data

Transient Signal Analysis (TSA) is a Go/No-Go device testing method that is based on the analysis of voltage tran-sients at multiple test points. In this paper, a technique based on an extension to TSA is presented that is able to predict critical path delay using data from non-critical (predictor) path tests. A characterization phase is performed a priori in which both predictor path and critical path delays are measured from a set of defect-free devices. The characterization data is used to define the relationship between the power supply transient signal data and the actual delays. Once established, prediction is performed during production test by simply re-analyzing the data from the predictor path Go/No-Go TSA tests, and therefore , no speed bin testing is required. Simulations on an 8-bit multiplier are used to demonstrate a linear relationship between a range of supply rail Fourier Phase harmonics and delay under various process models. The accuracy of the prediction is evaluated statistically against the measured delays from an additional set of critical path simulations. Transient Signal Analysis (TSA) is a parametric approach to testing digital integrated circuits [1][2]. In TSA, defect detection is accomplished by analyzing the transient signals measured at multiple test points on a device. The test points are located at or near the core logic supply pins on the device. By cross correlating the multiple test point measurements, a characterization profile of the device is obtained. The profile provides tolerance to process variation effects, and enhances the capacity of the method to distinguish between defect-free and defective devices. The power supply transients capture performance attributes of the device as well as pass/fail information. In this work, the performance information is analyzed for the purposes of predicting critical path delays. The basic idea is to reuse the data collected for the predictor path Go/ No-Go tests as a means of determining the maximum operational frequency of the device. This can reduce the cost and complexity of speed binning, a procedure that is routinely carried out on devices such as microprocessors. In order to show that such information exists in the power supply transient waveforms, a set of simulations were carried out on an 8-bit combinational multiplier. In these experiments, the delays to the outputs of the multi-plier were measured under 16 non-critical path test sequences. The experiments were repeated on circuit models that incorporated common variations in process parameters. The transient …