Study And Analysis Of Low Power Low Voltage Pipeline Architecture Of ADC Using 0.18 μm Technology

This paper is concerned with improving the efficiency of analog to digital converters (ADCs). the fast advancement of CMOS fabrication technology, more and more signalprocessing functions are implemented for a lower cost, lower power consumption, and higher yield. The design of analog-to-digital converters is one of the most critical and challenging aspects in the development of new and more powerful electronic systems, In this thesis design of 3 bit Pipeline ADC using 0.18 micrometer CMOS technology and The schematic of the various circuits drawn in Tanner SEdit and the simulation waveforms obtained using Tanner WEdit have been included.