Design and Analysis of a Hierarchical Clock Distribution System for Synchronous Standard Cell/Macrocell VLSI
نویسنده
چکیده
This paper describes the synebronous clock dktrfbution prob Iem in VLSI and techniques for its solution. In particular, a bierarcbicat design technique for minimizing clock skew within a VLSI circuit and its relative advantages and disadvantages is discussed. In addition, a model for clock distribution networks which considers the effects of dktributed interconnect impedances on clock skew is described.
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تاریخ انتشار 1999