PA-8000 Combines Complexity and Speed: 11/14/94

Long a proponent of simple, fast processors, HP has succumbed to the siren call of complexity, creating the most feature-filled RISC design yet revealed. Steve Manglesdorf, presenting at last month’s Microprocessor Forum, said that the forthcoming PA-8000 will achieve high clock rates despite the burden of this feature set, a powerful combination that he claims will create the industry’s fastest microprocessor. It will take quite some time, however, to validate this claim; HP does not expect system shipments for nearly 18 months. The new chip is similar to the MIPS R10000 (see 081403.PDF ) in its decoupled architecture with four-instruction dispatch and aggressive out-of-order execution. It goes beyond the MIPS design by adding dual floatingpoint units and dual load/store pipes as well as a larger out-of-order dispatch window. The most unusual feature is the total lack of on-chip cache; large external primary caches are an HP tradition but differ sharply from the designs used by other vendors. The PA-8000 will be the first HP chip to implement a 64-bit architecture, dubbed PA-RISC 2.0. Like other next-generation RISCs, the HP design initially will be expensive to produce, appearing first in servers and high-end workstations. A quick shrink is planned to bring cost to moderate levels while increasing performance. The first completely new processor design from HP since 1991, the PA-8000 and its derivatives will carry HP until the first fruits of its Intel alliance appear, probably around 1998. The new processor has not yet taped out; first silicon is expected early next year. Without seeing working parts, Manglesdorf was unwilling to disclose specific clock speed or performance targets for the PA-8000. He also declined to discuss physical details such as die area and package size. He did, however, provide an extensive description of the chip’s microarchitecture. PA-8000 Combines C