Trends in Low Power Digital System-on-Chip Designs (invited)

A study of the future trends in low-power System-on-Chip (SOC) designs is presented, based on the recently announced ITRS-2001 technology characteristics for both highperformance and low-power devices from 2001 to 2016. We forecast the logic/memory composition of a reference low-power PDA design with an area constraint of 1cm using both a bottom-up, power dissipation-constrained chip model and a top-down, design resourceconstrained model. Together, these analyses indicate that without accelerated improvements in both chip design productivity and leakage power management, future SOC designs will be comprised of 80-90% memory, with the remaining logic blocks composed of specialpurpose reusable IP cores, and a smaller fraction of the chip containing newly designed logic.