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سند علمی

Facilitating Low Power Scan Test in RTL Compiler

Priyanka Dasgupta, Vinayak Kadam, Vivek Chickermane, Sandeep Bhatia

چکیده

Low Power Design is a critical concern and metric for today's complex designs. During scan based manufacturing test, power dissipation becomes even more critical as the chip may not have been designed to tolerate excessive switching during scan test. Excessive power dissipation during scan test can result in excessive voltage variations, reduced noise margins and other signal integrity issues which could invalidate the test or may lead to premature chip failure. This presentation will highlight some of the power related issues during scan test. We will also demonstrate how the Cadence Encounter RTL Compiler provides a novel solution by estimating power dissipation during scan operation by analyzing the ATPG test patterns even before the complete DFT design is complete. Using this information, designers will be able to properly budget the power in their designs, and will be able to direct ATPG to limit switching activity during test.

اسناد مشابه

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