Turboscalar: A High Frequency High IPC Microarchitecture

There is significant performance motivation to build larger and wider superscalar machines, however the implementation complexity can be overwhelming. When superscalar machines grow they necessarily become deeper in order to maintain frequency. As the pipeline depth increases the performance gained by a wide instruction fetch and dispatch is lost to branch misprediction penalty cycles. This work proposes the new Turboscalar microarchitecture, which is strongly based on the superscalar paradigm. Turboscalar utilizes run time information to optimize instruction execution. This new microarchitecture increases performance by reducing implementation complexity, allowing the construction of very shallow wide pipelines, which yield high performance. Results: A realistic Turboscalar implementation is proposed, that improves performance 66% over a wide deep superscalar that utilizes a block-based trace cache.