Quasi-delay-insensitive Circuits Are Turing-complete

Delay Insensitive Circuits and Action Systems

The action systems formalism has been successfully used as a formal frame work for reasoning about concurrent behaviour Circuits both synchronous and asynchronous exhibit concurrent behaviour In this paper we com bine the design of asynchronous circuits with action systems We show how quasi delay insensitive circuits can be modelled as action systems This is done by de ning classes of action sy...

Delay-insensitive computation in asynchronous cellular automata

Asynchronous cellular automata (ACA) are cellular automata that allow cells to update their states independently at random times. Because of the unpredictability of the order of update, computing on ACA is usually done by simulating a timing mechanism to force all cells into synchronicity after which well-established synchronous methods of computation can be used. In this paper, we present a mo...

SEU-Tolerant QDI Circuits

This paper addresses the issue of Single-Event Upset (SEU) in quasi delay-insensitive (QDI) asynchronous circuits. We show that an SEU can cause abnormal computations in QDI circuits beside deadlock, and we propose a general method to make QDI circuits SEU-tolerant. We present a simplified SEUtolerant buffer implementations for CMOS technology. Finally, we present a case study of a one-bit comp...

Production Rule Veri cation for Quasi Delay Insensitive Circuits

Embedding Universal Delay-Insensitive Circuits in Asynchronous Cellular Spaces

Asynchronous Cellular Automata (ACA) are cellular automata which allow cells to be updated at times that are random and independent of each other. Due to their unpredictable behavior, ACA are usually dealt with by simulating a timing mechanism that forces all cells into synchronicity. Though this allows the use of well-established synchronous methods to conduct computations, it comes at the pri...