Delay-insensitive multi-ring structures

This paper describes a set of simple design and performance analysis techniques that have been successfully used to design a number of nontrivial delay insensitive circuits. Ezamples are building blocks for digital filters and a vector multiplier using a serialparallel multiply and accumulate algorithm. The vector multiplier circuit has been laid out, submitted for fabrication and successfully tested. Throughout the paper, elements from this design are used to illustrate the design and performance analysis techniques. The design technique is based on a data flow approach using pipelines and rings that are composed into larger multi-ring structures by joining and forking of signals. B y limiting to this class of structures, it is possible even for complez designs to analyze the performance and establish an understanding of the bottlenecks.