Design and Synthesis of 32 Bits Linear Feedback Shift Registers Architecture with Power Optimization

اسناد مشابه

• Design of efficient Linear Feedback Shift Register for BCH Encoder

  سند علمی۲۰۱۴S. Aiswarya, S. Aravinth, S. Uma

  The sequential circuit designed was Look-Ahead Transformation based LFSR in which a hardware complexity was present and it may limit their employ in many applications. The design of efficient LFSR for BCH encoder using TePLAT (Term Preserving Look-Ahead Transformation) overcame t

• Design of Efficient Linear Feedback Shift Register for BCH Encoder

  مقاله‌ی دسترسی آزاد۲۰۱۵Journal of Electrical & Electronic SystemsAiswarya SManikandan SK

• Bit Swapping Linear Feedback Shift Register For Low Power Application Using 130nm Complementary Metal Oxide Semiconductor Technology (TECHNICAL NOTE)

  مقاله۲۰۱۷International Journal of EngineeringFlorence Choong, Mamun Bin Ibne Reaz, Noorfazila Kamal, Norhafizan Binti Mohd Hanib

  Bit swapping linear feedback shift register (BS-LFSR) is employed in a conventional linear feedback shirt register (LFSR) to reduce its power dissipation and enhance its performance. In this paper, an enhanced BS-LFSR for low power application is proposed. To achieve low power di

• Design and Analysis of a Linear Feedback Shift Register with Reduced Leakage Power

  سند علمی۲۰۱۲Janaki Rani, S. Malarkkan, Adrian Nunez, Borivoje Nikolic

  As the CMOS technology is scaling down, leakage power has become one of the most critical design concerns for the chip designer. This paper proposes a low leakage linear feedback shift register that can be used in a crypto-processor. In this work, three bit, four bit and five bit

• A Design and Analysis of Low Power Linear Feedback Shift Register with Clock Gating

  سند علمی۲۰۱۶

  This paper presents a method to reduce the power consumption of the popular linear feedback shift register. The proposed scheme is based on the gated clock design approach and it can offer a significant power reduction, depending on technological characteristics of the employed g

• Power Optimization of Linear Feedback Shift Register Using Clock Gating

  سند علمی۲۰۱۳Yasmeen Khan

  A modified Linear Feedback Shift Register is designed in which power consumption reduction by deactivating the clock signal to Flip Flop when the output signal is same as input signal. The power consumption of the new LFSR is reduced due to the reduced switching of Flip Flop To v