Photoconductive-Sampling Time-Interleaved CMOS ADC

High speed analog-to-digital converters capable of digitizing signals with bandwidths of several tens of GHz have applications in high-speed instrumentation, wideband radar and optical communications. However, the design of converters with such high input bandwidths is constrained by the need for wideband sample-and-hold circuits with sufficiently low clock jitter. A number of photonic sampling techniques have been proposed to overcome the limitations of conventional electronic sampling circuits [1]. This work introduces a parallel ADC architecture, shown in Fig. 18.2.1, wherein a large number of time-interleaved photonic sampling channels each feed a 4b, 1GS/s CMOS ADC. The electrical input is sampled onto a hold capacitor using low-temperature-grown (LT) GaAs photoconductive switches that are optically triggered by a mode-locked laser generating sub-picosecond wide pulses at a 1GHz repetition rate. The output of the laser is split into multiple phase-delayed beams to drive the time-interleaved LT GaAs switches. The switches provide a sampling aperture of a few picoseconds with almost 6 bits of linearity and a sampling bandwidth greater than 50GHz [2]. The 4b ADC used to digitize each of the sampled signals is constrained by the need for a very low input capacitance and a small area, the latter necessary to allow the integration of many converters on a single chip to maximize the aggregate sampling rate. The use of optically triggered sampling and interleaving relaxes the jitter, timing skew and speed requirements of the electronic ADC’s.